1. Field of the Invention
The present invention relates to digital circuit designs utilizing delay lines for phase offset generation and comparison and more specifically relates to use of higher frequency clocks applied to a master delay lines used for calibrating associated slave delay lines. The higher frequency clock used with the master delay line permits shortening of the master delay line thereby improving its accuracy.
2. Discussion of Related Art
In most present in digital electronic circuits, clock signals are used to control and synchronize operation of the digital components to achieve the intended purpose, Clock signals inherently have an associated clock frequency and clock period. In a variety of digital circuit applications, it is necessary to generate desired phase offset relationships between signals associated with a common clock. For example, a first signals may be generated using a first phase relationship to a basic system clock while a second related signal may be generated with a second phase relationship from either the first signal or the common basic system clock. Similarly, it is often required that phase relationships be measured to detect relevant or desired phase relationships between two signals relative to a common system clock.
In generating or detecting such phase relationships relative to a basic system clock, it is common to use delay lines to establish a desired phase relationship delay between associated edges of the related digital signals. Such delay lines are comprised of a plurality of sequential delay elements each of which delays an input signal a predetermined fixed fraction of a clock period of the basic system clock from which the phase relationships are to be established. Each delay element of a plurality of delay elements is chained to a subsequent element (other than the final delay element). An appropriate number of such delay elements are chained together to create the desired delay necessary for achieving the desired phase relationship between a first signal and a second signal. For example, the first signal may be passed directly from the generating source to an intended recipient component whereas the second related signal is passed from its point of generation through an appropriate number of delay elements of a delay line and then on to its intended recipient component. The second signal being so delayed provides the desired phase relationship between the first and second signal.
Each delay element in such a chain of delay elements comprising a delay signal line has some inherent variability in its accuracy for imposing the specified delay amount. The design of digital circuits and the eventual layout and fabrication of a circuit having a delay line comprising multiple delay elements may impose further inaccuracies in the delay timing generated by such a delay line. For example, the layout of the delay elements in a particular delay line may introduce significant propagation delay between the chained delay elements of the delay line thus affecting the accuracy of the entire delay line.
It is generally known in the art to carefully layout and design circuits including delay line components so as to minimize the potential additional inaccuracy in such delay lines. Careful layout of a circuit design can help minimize propagation delays in a delay line. However, such care is difficult and often impractical in the design and fabrication of modern, complex integrated circuits. Further, the number of such delay lines in a complex integrated circuit may be substantial thereby further complicating any efforts to carefully layout and fabricate the circuit design so as to minimize propagation delays within delay line components.
One known technique for improving delay line accuracy is to provide a single delay line using the same delay elements as other delay lines but for which extra care is taken in the layout and fabrication so as to minimize additional inaccuracies in that particular delay line signal path. Such a carefully designed and fabricated delay line is often referred to as a xe2x80x9cmaster delay linexe2x80x9d or xe2x80x9creference delay line.xe2x80x9d The master delay line is then used in conjunction with calibration circuits to more precisely measure the delay required to achieve a particular desired phase relationship. Calibration information derived from such calibration circuits is then used in other operational delay lines within the circuit design to configure each operational delay line with reference to the more accurate master or reference delay line. These operational delay lines are often referred to as xe2x80x9cslave delay linesxe2x80x9d in that they are xe2x80x9cslavedxe2x80x9d to the master or reference delay line.
It remains a problem however to assure accuracy of even the master delay line. Even the most careful design layout and fabrication procedures may be inadequate to generate a highly precise master delay line. In particular, a long delay line (i.e., one comprised of a large number of delay elements) may entail unavoidable layout and fabrication problems. Regardless of the degree of care taken by the designer, a lengthy delay line may require compromises in circuit layout that may impose additional undesired inaccuracies in the master delay line.
It is evident from the above discussion that a need exists for methods and associated structure that provide additional accuracy in the design, layout and fabrication of master delay lines.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing methods and structure for the design of a master delay line using a higher frequency clock as compared to the base system clock used for associated slave delay lines. Use of a higher frequency clock in design of the master delay line permits the master delay line to be shortened by comparison to a master delay line using the same clock frequency as its associated slave delay lines. By so reducing the number of delay elements in the master delay line through use of the higher frequency clock, the accumulated inaccuracies (also referred to as xe2x80x9cstatic errorsxe2x80x9d or xe2x80x9cstatic phase errorsxe2x80x9d) is further reduced. The shorter master delay line may be more carefully designed, laid out and fabricated to minimize static errors induced by delay line propagation delays.
Slave delay lines associated with functional components of the overall circuit design and calibrated to the master delay line of the present invention operate on a slower clock than that associated with the master delay line. The slave delay lines therefore include a scaling or gear factor to adjust the calibrated reference configuration information to timing parameters of the slower frequency clock signal.
It is common in present-day circuit designs that a number of clock signals are available within the circuit. In a particular area of the circuit design, operational delay lines (slave delay lines) often utilize a common clock as the basis for their signal delay generation for phase offset and sensing features. Other clocks are generally readily available within the circuit design including common integer multiples of the frequency of the base clock used in functional components of the circuit and associated with slave delay lines. In this sense, the methods and structure of the present invention are applicable in any digital design where slave delay lines are calibrated to a master delay line and where multiple clocks of varying frequencies are available within the circuit design.
In one particular exemplary preferred embodiment, a DDR (double data rate) SDRAM memory controller integrated circuit often has a clock running at double the frequency of a base clock used within the memory controller for clocking the external memory devices. Application of the methods and structure of the present invention within such a DDR SDRAM memory controller permits the master delay line to be designed based upon the double (2xc3x97) frequency clock while slave delay lines, typically utilizing identical delay elements and calibrated from the master delay line, operate based upon the base clock frequency. The calibration information derived from the higher clock frequency master delay fine is xe2x80x9cgearedxe2x80x9d up to an appropriate configuration for the slower base clock frequency of the slave delay line. Such a design within a DDR SDRAM controller allows the master delay line to be approximately one-half the length of a master delay line devoid of the features of the present invention. The resulting reduction in the length of the master delay line enhances the accuracy of the master delay line by reducing accumulated static errors within the master delay line component. As noted, those skills in the art will recognize that a DDR SDRAM memory controller device is but one exemplary application of the methods and structure of the present invention. Further, those skills in the art will recognize that the higher frequency clock applied to the master delay line may be twice the base clock frequency as well as various other multiples, both integer and non-integer, of the base clock frequency.
A first aspect of the invention provides for a circuit comprising: a master delay line coupled to a first clock having a first clock frequency wherein the master delay line is comprised of a first plurality of delay elements; and a slave delay line used in conjunction with a second clock domain having a second clock frequency wherein the slave delay line is comprised of a second plurality of delay elements, wherein the first clock frequency is faster than the second clock frequency and wherein the slave delay line is calibrated to the master delay line.
A further aspect of the invention provides for master calibration logic for measuring a first number of delay elements of the first plurality of delay elements that in sequence provide a predetermined delay amount within the master delay line; and slave gear logic coupled to the master calibration logic for determining a second number of delay elements of the second plurality of delay elements that in sequence provide the predetermined delay amount within the slave delay line.
A still further aspect provides that the second clock frequency is a multiple of the first clock frequency and wherein the slave gear logic comprises: a multiplier to multiply the first number of delay elements by the multiple to determine the second number of delay elements.
In a second aspect, the invention provides a system comprising: a first clock having a first clock frequency; a master delay line coupled to the first dock and comprising a plurality of delay elements for selectively generating a predetermined master delay amount; master calibration logic coupled to the master delay line for providing a calibration value indicative or a number of delay elements selected within the master delay line to generate the predetermined master delay amount; and a plurality of slave components coupled to the master calibration logic wherein each slave component comprises: a slave delay line comprising a plurality of delay elements for selectively generating a predetermined slave delay amount; a second clock having a second clock frequency wherein the second clock frequency is less than the first clock frequency; slave functional circuits coupled to the second clock and coupled to the slave delay line to utilize the predetermined slave delay amount for generating a phase offset between a first signal and a second signal used within the slave functional circuits; and slave gear logic coupled to the master calibration logic and coupled to the slave delay line for determining from the calibration value a number of delay elements to be selected within the slave delay line to provide the predetermined slave delay amount.
Still another aspect of the invention provides a memory controller including: a first clock having a first clock frequency; a master delay line coupled to the first clock and comprising a plurality of delay elements for selectively generating a predetermined master delay amount; master calibration logic coupled to the master delay line for providing a calibration value indicative or a number of delay elements selected within the master delay line to generate the predetermined master delay amount; and a plurality of slave components coupled to the master calibration logic wherein each slave component comprises: a slave delay line comprising a plurality of delay elements for selectively generating a predetermined slave delay amount; a second clock having a second clock frequency wherein the second clock frequency is approximately half of the first clock frequency; slave functional circuits coupled to the second clock and coupled to the slave delay line to utilize the predetermined slave delay amount for generating a phase offset between a first signal and a second signal used within the slave functional circuits; and slave gear logic coupled to the master calibration logic and coupled to the slave delay line for determining from the calibration value a number of delay elements to be selected within the slave delay line to provide the predetermined slave delay amount.
Another aspect further provides that the slave gear logic comprises: a multiplier for multiplying the calibration value by two to determine the number of delay elements selected within the salve delay line to generate the predetermined slave delay amount.
In yet another aspect, the invention provides a method operable with a circuit having a first clock, a second clock, a master delay line coupled to the first clock and a slave component coupled to the second clock wherein the second clock has a lower frequency than the first clock and wherein the slave component includes a slave delay line, the method comprising the steps of: calibrating the master delay line to determine a calibration value indicating a number of delay elements within the master delay line required to generate a predetermined master delay amount; determining from the calibration value a corresponding number of delay elements within the slave delay line required to generate a predetermined slave delay amount; and selecting the number of delay elements within the slave delay line to generate the predetermined slave delay amount from the slave delay line.
Another aspect of the method provides that the step of determining includes the step of: multiplying the calibration value by a multiplier value to determine the number of delay elements within the slave delay line.
Still another aspect of the method provides that the step of multiplying includes the step of: multiplying the calibration value by a value substantially equal to the ratio of the first clock frequency to the second clock frequency.